//-----------------Module_logic_gates---------------//
module logic_gates(
    input CLK_12M,
    output c,
    output d,
    output e,
    output f,
    output g,
    output h,
    output i,
    output j,
    output k,
    output l
);

//-----------------------rst_n----------------------//    
    reg rst_n;
    reg [3:0]cnt_rst;
    
    always@(posedge CLK_12M)
        begin
            if(cnt_rst==4'd10)
                begin
                    rst_n <= 1'd1;
                    cnt_rst <= 4'd10;
                end
            else cnt_rst <= cnt_rst + 1'd1;
        end

//--------------------signal_a---------------------//                
    reg [7:0]a;    
    
    always@(posedge CLK_12M or negedge rst_n) //产生输入信号a
        begin
            if(!rst_n)
                a <= 8'd0;
            else if(a == 8'd255)
                a <= 8'd0;
            else a <= a + 1'd1;
        end
        
//---------------------signal_b----------------------//                                    
    reg [9:0]b;        
    
    always@(posedge CLK_12M or negedge rst_n) //产生输入信号b
        begin
            if(!rst_n)
                b <= 10'd0;
            else if(b == 10'd1023)
                b <= 10'd0;
            else b <= b + 1'd1;    
        end
        
//----------------------逻辑运算----------------------//        
    assign c = a[7] && b[9];            //逻辑与
    assign d = a[7] || b[9];            //逻辑或
    assign e = !a[7];                        //逻辑非
    
//-----------------------位运算----------------------//    
    assign f = a[7] & b[9];                //按位与
    assign g = a[7] | b[9];                //按位或
    assign h = ~a[7];                        //按位非
    assign i = a[7] &~ b[9];            //按位与非
    assign j = a[7] |~ b[9];            //按位或非
    assign k = a[7] ^ b[9];                //按位异或
    assign l = a[7] ~^ b[9];            //按位同或
    
//-----------------------endmodule-------------------//        
endmodule