module signal_ctrl(
    input clk_25m,
    input rst_n,
    output fpga_ledr,
    output fpga_ledg,
    output fpga_ledb
);
//--------------------cnt_led-------------------------------//    
reg led_clk;

always @(posedge clk_25m or negedge rst_n)
    if (!rst_n)
        begin
            led_clk <= 1'd0;
            cnt_led <= 25'd0;
        end
    else if(cnt_led == 25'd8000000)
        begin
            cnt_led <= 25'd0;
            led_clk <= ~led_clk;
        end
    else cnt_led <= cnt_led + 1'd1;

//--------------------led----------------------------------//            
reg [2:0]led;
reg [24:0]cnt_led;

always @(posedge led_clk or negedge rst_n)
    if (!rst_n)
        begin
            led <= 3'd1;
        end
    else
        begin
            if (led[2])
                begin
                    led <= 3'd1;
                end
            else 
                begin
                    led <= led << 1'd1;
                end
        end

assign {fpga_ledr,fpga_ledg,fpga_ledb} = ~led;

//--------------------endmodule--------------------------//    
endmodule