Verilog project-猿圈-程序猿的知识社区

This is a most popular repository list for Verilog sorted by number of stars

STARS	FORKS	ISSUES	LAST COMMIT	NAME/PLACE	DESCRIPTION
1450	676	33	1 year, 1 month ago	e200_opensource/1	The Ultra-Low Power RISC Core
1371	362	27	5 months ago	picorv32/2	PicoRV32 - A Size-Optimized RISC-V CPU
1157	399	23	10 months ago	wujian100_open/3	IC design and development should be faster，simpler and more reliable
936	371	176	2 years ago	hw/4	RTL, Cmodel, and testbench for NVDLA
930	61	2	1 year, 6 months ago	amiga2000-gfxcard/5	MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
886	119	7	20 hours ago	darkriscv/6	opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
618	160	10	3 years ago	miaow/7	An open source GPU based off of the AMD Southern Islands ISA.
615	921	25	a day ago	hdl/8	HDL libraries and projects
581	70	0	2 months ago	zipcpu/9	A small, light weight, RISC CPU soft core
573	199	16	16 hours ago	verilog-ethernet/10	Verilog Ethernet components for FPGA implementation
547	194	30	2 years ago	oh/11	Verilog library for ASIC and FPGA designers
487	426	38	23 days ago	uhd/12	The USRP™ Hardware Driver Repository
475	87	11	2 hours ago	corundum/13	Open source, high performance, FPGA-based NIC
409	192	6	1 year, 10 months ago	ODriveHardware/14	High performance motor control
400	138	4	5 months ago	open-fpga-verilog-tutorial/15	Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
387	86	38	3 days ago	sd2snes/16	SD card based multi-purpose cartridge for the SNES
384	149	1	3 years ago	mips-cpu/17	MIPS CPU implemented in Verilog
360	71	0	9 months ago	LeFlow/18	Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
317	116	24	2 months ago	mor1kx/19	mor1kx - an OpenRISC 1000 processor IP core
294	139	0	5 years ago	FPGA-Imaging-Library/20	An open source library for image processing on FPGA.
289	151	37	4 years ago	riffa/21	The RIFFA development repository
286	48	11	4 months ago	riscv-formal/22	RISC-V Formal Verification Framework
270	96	0	2 years ago	verilog/23	Repository for basic (and not so basic) Verilog blocks with high re-use potential
269	89	7	1 year, 4 months ago	icezum/24	? IceZUM Alhambra: an Arduino-like Open FPGA electronic board
267	124	14	8 years ago	netfpga/25	NetFPGA 1G infrastructure and gateware
255	43	8	4 days ago	serv/26	SERV - The SErial RISC-V CPU
252	86	4	a month ago	verilog-axi/27	Verilog AXI components for FPGA implementation
250	37	8	3 months ago	VerilogBoy/28	A Pi emulating a GameBoy sounds cheap. What about an FPGA?
243	27	7	1 year, 4 months ago	Project-Zipline/29	Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
235	114	6	6 years ago	FPGA-Litecoin-Miner/30	A litecoin scrypt miner implemented with FPGA on-chip memory.
213	54	2	2 years ago	zet/31	Open source implementation of a x86 processor
210	96	16	2 years ago	convolution_network_on_FPGA/32	CNN acceleration on virtex-7 FPGA with verilog HDL
209	20	65	7 months ago	ucr-eecs168-lab/33	The lab schedules for EECS168 at UC Riverside
198	85	2	3 months ago	cores/34	Various HDL (Verilog) IP Cores
194	21	20	1 year, 6 days ago	spispy/35	An open source SPI flash emulator and monitor
193	37	1	3 years ago	ridecore/36	RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
190	53	32	24 days ago	OpenROAD/37	OpenROAD's unified application implementing an RTL-to-GDS Flow
190	69	0	a month ago	basic_verilog/38	Must-have verilog systemverilog modules
190	46	1	5 months ago	riscv/39	RISC-V CPU Core (RV32IM)
189	30	4	6 days ago	Flute/40	RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
184	69	13	11 months ago	fpu/41	synthesiseable ieee 754 floating point library in verilog
183	49	22	8 years ago	fpga_nes/42	FPGA-based Nintendo Entertainment System Emulator
181	62	1	4 years ago	verilog-6502/43	A Verilog HDL model of the MOS 6502 CPU
179	35	13	a month ago	Piccolo/44	RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
174	64	6	16 hours ago	verilog-pcie/45	Verilog PCI express components
173	58	10	5 months ago	Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/46	Verilog Generator of Neural Net Digit Detector for FPGA
168	7	1	1 year, 9 months ago	fpga-chip8/47	CHIP-8 console on FPGA
165	169	1	4 months ago	fpga/48	The USRP™ Hardware Driver FPGA Repository
163	26	5	2 years ago	TinyFPGA-B-Series/49	Open source design files for the TinyFPGA B-Series boards.
162	21	0	6 years ago	ez8/50	The Easy 8-bit Processor
156	37	94	6 hours ago	basejump_stl/51	BaseJump STL: A Standard Template Library for SystemVerilog
155	10	0	11 months ago	fpg1/52	PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.
153	32	14	6 hours ago	openlane/53	OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
150	52	1	3 years ago	sdram-controller/54	Verilog SDRAM memory controller
146	47	3	10 months ago	AccDNN/55	A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
146	59	2	1 year, 4 months ago	verilog-i2c/56	Verilog I2C interface for FPGA implementation
145	65	0	2 months ago	Kryon/57	FPGA,Verilog,Python
142	61	4	1 year, 6 months ago	verilog-uart/58	Verilog UART
137	53	2	6 months ago	sha256/59	Hardware implementation of the SHA-256 cryptographic hash function
137	50	3	2 years ago	CNN-FPGA/60	使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
133	20	1	9 days ago	wb2axip/61	Bus bridges and other odds and ends
127	102	114	3 months ago	black-parrot/62	A Linux-capable host multicore for and by the world
124	38	0	6 years ago	milkymist/63	SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
123	24	0	1 year, 10 months ago	SimpleVOut/64	A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
122	23	4	11 months ago	FPGA-peripherals/65	? ❄️ Collection of open-source peripherals in Verilog
119	41	5	1 year, 2 months ago	Tang_E203_Mini/66	LicheeTang 蜂鸟E203 Core
118	66	3	3 years ago	FPGA_Based_CNN/67	FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
118	44	2	a month ago	SCALE-MAMBA/68	Repository for the SCALE-MAMBA MPC system
116	25	0	a month ago	wbuart32/69	A simple, basic, formally verified UART controller
113	41	3	6 years ago	fpganes/70	NES in Verilog
113	41	19	11 months ago	open-register-design-tool/71	Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
110	20	5	1 year, 6 months ago	DisplayPort_Verilog/72	A Verilog implementation of DisplayPort protocol for FPGAs
110	51	0	27 days ago	openwifi-hw/73	FPGA/hardware design of openwifi
110	77	16	2 years ago	orpsoc-cores/74	Core description files for FuseSoC
108	57	0	5 days ago	aes/75	Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
107	41	0	22 days ago	schoolMIPS/76	CPU microarchitecture, step by step
106	58	5	a month ago	openofdm/77	Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
106	26	1	23 days ago	iceGDROM/78	An FPGA based GDROM emulator for the Sega Dreamcast
105	10	0	2 years ago	vm80a/79	i8080 precise replica in Verilog, based on reverse engineering of real die
102	30	3	a day ago	nandland/80	All code found on nandland is here. underconstruction.gif
101	27	0	2 years ago	mriscv/81	A 32-bit Microcontroller featuring a RISC-V core
100	43	1	8 years ago	fft-dit-fpga/82	Verilog module for calculation of FFT.
98	14	3	a month ago	DreamcastHDMI/83	Dreamcast HDMI
98	26	2	6 months ago	RePlAce/84	RePlAce global placement tool
97	68	4	3 years ago	Hardware-CNN/85	A convolutional neural network implemented in hardware (verilog)
97	29	2	2 years ago	Single_instruction_cycle_OpenMIPS/86	通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
97	70	4	7 years ago	uvm_axi/87	uvm AXI BFM(bus functional model)
96	16	0	19 days ago	a2o/88	None
96	13	58	1 year, 10 months ago	spatial-lang/89	Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
95	17	17	a day ago	livehd/90	Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
95	19	3	5 months ago	biriscv/91	32-bit Superscalar RISC-V CPU
95	12	1	2 months ago	cpu11/92	Revengineered ancient PDP-11 CPUs, originals and clones
94	61	1	4 years ago	or1200/93	OpenRISC 1200 implementation
93	20	3	11 days ago	warp-v/94	WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
93	17	1	5 years ago	oldland-cpu/95	Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
92	29	1	3 years ago	kamikaze/96	Light-weight RISC-V RV32IMC microcontroller core.
90	18	0	3 years ago	archexp/97	浙江大学计算机体系结构课程实验
90	12	3	10 months ago	panologic-g2/98	Pano Logic G2 Reverse Engineering Project
86	29	2	2 months ago	apple-one/99	An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
85	23	0	10 months ago	mips32-cpu/100	奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
85	14	2	11 months ago	raven-picorv32/101	Silicon-validated SoC implementation of the PicoSoc/PicoRV32
86	22	1	28 days ago	ice40-playground/102	Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
84	9	1	1 year, 10 months ago	NeoGeoFPGA-sim/103	Simulation only cartridge NeoGeo hardware definition
83	29	0	3 days ago	ivtest/104	Regression test suite for Icarus Verilog.
82	76	0	2 years ago	FPGA-CNN/105	FPGA implementation of Cellular Neural Network (CNN)
82	16	3	5 years ago	NeoGeoHDMI/106	Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI
81	5	0	a month ago	vgasim/107	A Video display simulator
80	36	8	1 year, 3 months ago	mipsfpga-plus/108	MIPSfpga+ allows loading programs via UART and has a switchable clock
80	16	0	3 months ago	openarty/109	An Open Source configuration of the Arty platform
79	29	1	7 years ago	Xilinx-Serial-Miner/110	Bitcoin miner for Xilinx FPGAs
79	10	4	13 days ago	n64rgb/111	Everything around N64 and RGB
79	35	8	10 months ago	Tang_FPGA_Examples/112	LicheeTang FPGA Examples
78	10	1	3 months ago	lpc_sniffer_tpm/113	A low pin count sniffer for ICEStick - targeting TPM chips
78	20	15	2 years ago	c65gs/114	FPGA-based C64 Accelerator / C65 like computer
78	8	1	9 years ago	Homotopy/115	Homotopy theory in Coq.
78	8	0	2 years ago	iCE40/116	Lattice iCE40 FPGA experiments - Work in progress
78	18	1	9 months ago	usbcorev/117	A full-speed device-side USB peripheral core written in Verilog.
78	34	18	8 days ago	Hermes-Lite2/118	A second generation low-cost amateur HF software defined radio transceiver.
77	26	0	9 months ago	NaiveMIPS-HDL/119	Naïve MIPS32 SoC implementation
77	24	0	5 years ago	lm32/120	LatticeMico32 soft processor
77	18	3	3 months ago	tinyfpga_bx_usbserial/121	USB Serial on the TinyFPGA BX
76	23	0	5 years ago	cpu/122	A very primitive but hopefully self-educational CPU in Verilog
76	44	65	8 hours ago	fomu-workshop/123	Support files for participating in a Fomu workshop
76	7	3	5 hours ago	jt12/124	FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
75	11	3	4 years ago	fpgaboy/125	Implementation Nintendo's GameBoy console on an FPGA
75	7	4	a month ago	usb3_pipe/126	USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5
75	43	3	7 years ago	Icarus/127	DUAL Spartan6 Development Platform
74	11	1	4 months ago	Toooba/128	RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
74	7	1	5 months ago	antikernel/129	The Antikernel operating system project
72	18	0	a month ago	icebreaker-examples/130	This repository contains small example designs that can be used with the open source icestorm flow.
70	9	0	4 years ago	PonyLink/131	A single-wire bi-directional chip-to-chip interface for FPGAs
70	12	1	3 days ago	Radioberry-2.x/132	Ham Radio hat for Raspberry PI
70	12	0	7 months ago	agc_simulation/133	Verilog simulation files for a replica of the Apollo Guidance Computer
69	7	1	6 months ago	display_controller/134	FPGA display controller with support for VGA, DVI, and HDMI.
69	19	7	4 months ago	ice40_examples/135	Public examples of ICE40 HX8K examples using Icestorm
68	30	24	4 days ago	ao486_MiSTer/136	ao486 port for MiSTer
68	46	4	6 years ago	DSLogic-hdl/137	An open source FPGA design for DSLogic
67	7	1	18 hours ago	icestation-32/138	Compact FPGA game console
67	41	18	2 months ago	Genesis_MiSTer/139	Sega Genesis for MiSTer
67	27	0	1 year, 8 months ago	PASC/140	Parallel Array of Simple Cores. Multicore processor.
66	28	0	3 months ago	Verilog-Practice/141	HDLBits website practices & solutions
65	4	4	a month ago	RISCBoy/142	Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
65	8	8	2 months ago	xcrypto/143	XCrypto: a cryptographic ISE for RISC-V
64	28	8	1 year, 1 month ago	c5soc_opencl/144	DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
63	17	2	1 year, 9 months ago	ZAP/145	ZAP is a pipelined ARMv4T architecture compatible processor with cache and MMU.
62	11	0	4 years ago	cpus-caddr/146	FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
62	32	1	2 years ago	zynq-axis/147	Hardware, Linux Driver and Library for the Zynq AXI DMA interface
62	14	5	1 year, 1 month ago	Reindeer/148	PulseRain Reindeer - RISCV RV32I[M] Soft CPU
61	9	3	30 days ago	jt_gng/149	CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando and Vulgus.
60	14	0	1 year, 3 days ago	MobileNet-in-FPGA/150	Generator of verilog description for FPGA MobileNet implementation
59	16	6	8 months ago	Haasoscope/151	Docs, design, firmware, and software for the Haasoscope
58	13	3	8 years ago	ao68000/152	The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
58	22	18	a day ago	Minimig-AGA_MiSTer/153	None
58	7	0	3 years ago	FPGA-TX/154	FPGA based transmitter
58	8	0	2 years ago	toygpu/155	A simple GPU on a TinyFPGA BX
57	8	1	11 months ago	Riscy-SoC/156	Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
57	9	0	1 year, 1 month ago	MIPS-pipeline-processor/157	A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
56	23	1	2 years ago	VidorFPGA/158	repository for Vidor FPGA IP blocks and projects
55	30	19	8 days ago	NeoGeo_MiSTer/159	NeoGeo for MiSTer
54	23	2	5 months ago	SD-card-controller/160	WISHBONE SD Card Controller IP Core
54	7	13	1 year, 3 months ago	Neogeo_MiSTer_old/161	SNK NeoGeo core for the MiSTer platform
54	13	0	4 months ago	hardenedlinux_profiles/162	It contains hardenedlinux community documentation.
53	24	0	a month ago	cdbus_ip/163	CDBUS Protocol and the IP Core for FPGA users
53	18	0	2 years ago	clacc/164	Deep Learning Accelerator (Convolution Neural Networks)
52	25	0	a month ago	timetoexplore/165	Source code to accompany https://timetoexplore.net
52	13	0	4 years ago	fpga-md5-cracker/166	A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.
52	17	14	1 year, 28 days ago	alpha-release/167	Builds, flow and designs for the alpha release
52	9	1	7 months ago	ice40_ultraplus_examples/168	Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
51	30	0	7 years ago	uart/169	Verilog UART
51	11	0	1 year, 5 months ago	MARLANN/170	Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
51	4	2	10 months ago	ay-3-8910_reverse_engineered/171	The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.
50	7	0	1 year, 4 months ago	up5k_basic/172	A small 6502 system with MS BASIC in ROM
50	21	1	10 months ago	opencpi/173	Open Component Portability Infrastructure
50	20	51	5 days ago	bsg_manycore/174	Tile based architecture designed for computing efficiency, scalability and generality
50	22	0	2 years ago	verilog-lfsr/175	Fully parametrizable combinatorial parallel LFSR/CRC module
50	47	5	2 years ago	Convolutional-Neural-Network/176	Implementation of CNN using Verilog
50	13	0	1 year, 9 months ago	VexRiscvSoftcoreContest2018/177	None
50	28	34	4 years ago	minimig-mist/178	Minimig for the MiST board
49	28	0	a month ago	cdpga/179	FPGA core boards / evaluation boards based on CDCTL hardware
49	9	0	1 year, 11 months ago	riscv/180	Verilog implementation of a RISC-V core
48	11	3	19 days ago	aib-phy-hardware/181	Advanced Interface Bus (AIB) die-to-die hardware open source
48	2	0	1 year, 6 months ago	soc/182	An experimental System-on-Chip with a custom compiler toolchain.
47	15	0	6 years ago	verilog_fixed_point_math_library/183	Fixed Point Math Library for Verilog
46	40	1	a month ago	Practical-UVM-Step-By-Step/184	This is the main repository for all the examples for the book Practical UVM
46	22	3	3 years ago	digital-servo/185	NIST digital servo: an FPGA based fast digital feedback controller
45	3	1	3 years ago	21FX/186	A bootloader for the SNES console
46	14	0	2 years ago	hyperram/187	Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
46	20	2	1 year, 4 days ago	daisho/188	Test of the USB3 IP Core from Daisho on a Xilinx device
45	14	1	8 months ago	aib-phy-hardware/189	None
45	9	1	2 years ago	RISC-V-CPU/190	RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
45	10	1	1 year, 5 months ago	up5k/191	Upduino v2 with the ice40 up5k FPGA demos
45	33	1	5 years ago	mips32r1_xum/192	A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old University of Utah XUM archive)
44	3	0	21 days ago	wbscope/193	A wishbone controlled scope for FPGA's
44	26	2	6 years ago	beagle/194	BeagleBone HW, SW, & FPGA Development
44	3	0	2 years ago	collection-iPxs/195	Icestudio Pixel Stream collection
44	14	0	2 years ago	SoftMC/196	SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf
44	17	2	2 years ago	chiphack/197	Repository and Wiki for Chip Hack events.
44	5	0	2 months ago	XilinxUnisimLibrary/198	None
44	15	3	8 years ago	ORGFXSoC/199	An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
44	7	47	21 days ago	rigel/200	Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
43	22	8	3 years ago	nysa-sata/201	None
44	20	0	2 years ago	TOE/202	TCP Offload Engine
43	24	0	25 days ago	async_fifo/203	A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
43	17	0	2 years ago	MIPS/204	A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
43	4	0	1 year, 5 months ago	rt/205	A Full Hardware Real-Time Ray-Tracer
42	4	1	8 months ago	flickerfixer/206	An open source flicker fixer for Amiga 500/2000
41	37	1	1 year, 3 months ago	AlteraDE2Labs_Verilog/207	My solutions to Alteras example labs
41	15	0	5 years ago	Verilog-caches/208	Various caches written in Verilog-HDL
41	10	0	3 years ago	mc6809/209	Cycle-Accurate MC6809/E implementation, Verilog
40	7	0	4 years ago	MAM65C02-Processor-Core/210	Microprogrammed 65C02-compatible Processor Core for FPGAs (Verilog-2001)
40	21	1	a month ago	libsystemctlm-soc/211	SystemC/TLM-2.0 Co-simulation framework
40	5	1	1 year, 2 months ago	engine-V/212	SoftCPU/SoC engine-V
40	13	0	4 years ago	yarvi/213	Yet Another RISC-V Implementation
39	7	15	2 days ago	hrm-cpu/214	Human Resource Machine - CPU Design #HRM
39	5	1	2 years ago	lpc_sniffer/215	a low pin count sniffer for icestick
39	8	0	3 months ago	moxie-cores/216	Moxie-compatible core repository
39	3	1	a month ago	iua/217	ice40 USB Analyzer
39	12	0	4 years ago	sds7102/218	A port of Linux to the OWON SDS7102 scope
38	19	1	2 months ago	cnn_hardware_acclerator_for_fpga/219	This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
38	10	0	1 year, 5 months ago	Speech256/220	An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
38	26	1	1 year, 8 months ago	GNSS_Firehose/221	Wideband front-end digitizer for GPS, GLONASS, Galileo, BeiDou
38	7	1	11 months ago	panologic/222	PanoLogic Zero Client G1 reverse engineering info
37	9	0	1 year, 3 months ago	ctf/223	Stuff from CTF contests
37	30	0	5 years ago	mojo-base-project/224	This is the base project for the Mojo. It should be used as the starting point for all projects.
37	6	0	5 months ago	MIPS48PipelineCPU/225	冯爱民老师《计算机组成原理A》课程设计
37	7	0	3 years ago	mips-cpu/226	A MIPS CPU implemented in Verilog
37	14	0	11 months ago	R8051/227	8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
37	12	2	1 year, 4 months ago	Verilog-Projects/228	This repository contains source code for past labs and projects involving FPGA and Verilog based designs
37	10	0	3 months ago	challenges-2020/229	Pwn2Win 2020 Challenges
37	21	2	1 year, 2 months ago	verilog-cam/230	Verilog Content Addressable Memory Module
37	6	2	9 months ago	OpenAmiga500FastRamExpansion/231	4/8 MB Fast RAM Expansion for the Commodore Amiga 500
36	8	2	4 years ago	ACC/232	Apollo CPU Core in Verilog. For learning and having fun with open FPGA
36	7	2	2 years ago	cnnhwpe/233	None
36	12	1	5 months ago	fpga-sdft/234	sliding DFT for FPGA, targetting Lattice ICE40 1k
36	12	0	4 months ago	sha3/235	None
36	9	0	8 years ago	dcpu16/236	Pipelined DCPU-16 Verilog Implementation
35	16	1	2 years ago	ARM7/237	Implemetation of pipelined ARM7TDMI processor in Verilog
35	2	0	2 years ago	vga_to_ascii/238	Realtime VGA to ASCII Art converter
35	29	1	2 years ago	ethernet_10ge_mac_SV_UVM_tb/239	SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
35	18	18	17 days ago	MegaCD_MiSTer/240	Mega CD for MiSTer
35	9	0	1 year, 8 months ago	HyperBUS/241	A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
35	7	9	1 year, 11 months ago	BeagleWire/242	This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017
35	12	0	3 years ago	caribou/243	Caribou: Distributed Smart Storage built with FPGAs
35	4	0	2 years ago	RISC-processor/244	Simple single cycle RISC processor written in Verilog
35	24	3	2 years ago	prog_fpgas/245	The repository for the Verilog code examples and ISE projects that accompany the book Programming FPGAs: Getting Started with Verilog.
35	16	1	5 years ago	minimig-de1/246	Minimig for the DE1 board
34	13	0	7 years ago	Multiplier16X16/247	Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
34	11	5	5 days ago	mflowgen/248	mflowgen -- A Modular ASIC/FPGA Flow Generator
34	11	0	4 months ago	max1000-tutorial/249	Tutorial and example projects for the Arrow MAX1000 FPGA board
34	10	0	9 months ago	icebreaker-workshop/250	iCEBreaker Workshop
34	7	1	2 years ago	BAR-Tender/251	An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver
34	21	3	4 years ago	bch_verilog/252	Verilog based BCH encoder/decoder
33	12	1	8 years ago	vSPI/253	Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
33	6	0	28 days ago	rsyocto/254	? SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
33	19	1	3 years ago	h.265_encoder/255	None
33	7	3	a month ago	iceZ0mb1e/256	FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
32	13	0	5 years ago	verilog-utils/257	native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
32	11	1	12 days ago	fusesoc-cores/258	FuseSoC standard core library
32	5	0	1 year, 4 months ago	fpga-odysseus/259	FPGA Odysseus with ULX3S
32	4	2	3 years ago	Frix/260	IBM PC Compatible SoC for a commercially available FPGA board
32	18	0	2 years ago	mnist_fpga/261	using xilinx xc6slx45 to implement mnist net
32	19	0	1 year, 10 months ago	huaweicloud-fpga/262	The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
32	7	0	7 months ago	dpll/263	A collection of phase locked loop (PLL) related projects
31	12	2	6 months ago	h265-encoder-rtl/264	None
31	16	1	17 years ago	8051/265	8051 core
31	18	1	2 years ago	GnuRadar/266	Open-source software defined radar based on the USRP 1 hardware.
31	13	0	2 years ago	robot-arm-v01/267	None
31	2	0	5 years ago	gb/268	The Original Nintendo Gameboy in Verilog
31	8	3	5 months ago	tinyriscv/269	A very simple and easy to understand RISC-V core.
31	6	0	3 years ago	wiki/270	None
31	13	0	7 years ago	fpganes/271	FPGA-based AI for Super Mario Bros. Designed for an Altera DE2
31	10	0	9 months ago	drec-fpga-intro/272	Materials for "Introduction to FPGA and Verilog" at MIPT DREC
30	5	1	5 years ago	oc_jpegencode/273	Fork of OpenCores jpegencode with Cocotb testbench
30	27	0	5 years ago	IPCORE/274	None
30	1	2	10 months ago	spokefpga/275	FPGA Tools and Library
30	26	3	6 years ago	cordic/276	An implementation of the CORDIC algorithm in Verilog.
30	24	0	8 years ago	DDR2_Controller/277	DDR2 memory controller written in Verilog
29	3	0	1 year, 10 months ago	riscv-megaproject/278	A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones
29	2	0	4 years ago	HaSKI/279	Cλash/Haskell FPGA-based SKI calculus evaluator
29	5	0	2 years ago	OpenFPGA/280	OpenFPGA
29	10	3	a month ago	verilog-math/281	Mathematical Functions in Verilog
29	21	0	3 months ago	thinpad_top/282	Project template for Artix-7 based Thinpad board
29	3	0	1 year, 8 months ago	tiny_usb_examples/283	Using the TinyFPGA BX USB code in user designs
29	5	0	2 years ago	screen-pong/284	Pong game in a free FPGA.
29	34	1	5 days ago	oc-accel/285	OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
29	21	2	4 days ago	blinky/286	Example LED blinking project for your FPGA dev board of choice
28	5	0	2 years ago	DIY_OpenMIPS/287	實作《自己動手寫CPU》書上的程式碼
28	8	3	4 months ago	i3c-slave-design/288	MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
28	3	1	12 days ago	VGChips/289	Video Game custom chips reverse-engineered from silicon
28	3	3	4 months ago	observer/290	None
28	10	0	1 year, 2 months ago	csirx/291	Open-source CSI-2 receiver for Xilinx UltraScale parts
28	18	1	7 years ago	Atalanta/292	Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
28	10	41	23 days ago	zx-evo/293	TS-Configuration for ZX Spectrum clone named ZX-Evolution
28	3	0	2 years ago	Computer-Architecture-Task-2/294	Riscv32 CPU Project
28	5	2	a day ago	ice-chips-verilog/295	IceChips is a library of all common discrete logic devices in Verilog
28	7	0	2 months ago	first-fpga-pcb/296	FPGA dev board based on Lattice iCE40 8k
28	9	0	4 months ago	MangoMIPS32/297	A softcore microprocessor of MIPS32 architecture.
28	4	0	6 years ago	CPU32/298	Tiny MIPS for Terasic DE0
27	14	0	2 years ago	eddr3/299	mirror of https://git.elphel.com/Elphel/eddr3
27	12	0	4 years ago	yosys-bigsim/300	A collection of big designs to run post-synthesis simulations with yosys
27	12	0	4 years ago	yosys-bigsim/301	A collection of big designs to run post-synthesis simulations with yosys
27	23	3	28 days ago	Menu_MiSTer/302	None
27	12	51	4 months ago	tapasco/303	The Task Parallel System Composer (TaPaSCo)
27	31	0	6 years ago	FPGA_image_processing/304	Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image
27	15	0	8 years ago	verilog-sha256/305	Implementation of the SHA256 Algorithm in Verilog
27	17	0	1 year, 6 months ago	x393/306	mirror of https://git.elphel.com/Elphel/x393
27	17	0	8 years ago	tdc-core/307	A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
27	3	1	4 years ago	RISCV_Piccolo_v1/308	Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
27	3	2	3 days ago	QuokkaEvaluation/309	Example projects for Quokka FPGA toolkit
27	9	0	1 year, 4 months ago	BUAA_CO/310	2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
26	13	1	1 year, 7 days ago	ethmac/311	Ethernet MAC 10/100 Mbps
26	3	0	2 years ago	s6soc/312	CMod-S6 SoC
26	8	17	8 days ago	symbiflow-examples/313	Examples designs for showing different ways to use SymbiFlow toolchains.
26	5	2	1 year, 9 months ago	iCEstick-UART-Demo/314	This is a simple UART echo test for the iCEstick Evaluation Kit
26	8	0	5 months ago	LUTNet/315	None
26	13	0	4 years ago	peridot/316	'PERIDOT' - Simple & Compact FPGA board
26	6	0	2 days ago	trng/317	True Random Number Generator core implemented in Verilog.
26	15	0	7 years ago	rfid-verilog/318	RFID tag and tester in Verilog
25	21	0	5 years ago	CNN_FPGA/319	verilog CNN generator for FPGA
25	3	2	8 months ago	zbasic/320	A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
25	16	0	3 years ago	HitchHike/321	None
25	8	0	6 years ago	vj-uart/322	Virtual JTAG UART for Altera Devices
25	13	1	2 years ago	openmsp430/323	The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
25	9	0	4 days ago	myslides/324	Collection of my presentations
25	5	2	8 months ago	datc_robust_design_flow/325	DATC Robust Design Flow.
25	2	4	11 months ago	quark/326	Stack CPU ? Work In Progress ?
25	14	0	5 years ago	Video-and-Image-Processing-Design-Using-FPGAs/327	Video and Image Processing
25	10	0	3 years ago	ECE1373_2016_hft_on_fpga/328	High Frequency Trading using Vivado HLS
25	6	0	2 months ago	jt49/329	Verilog clone of YM2149
25	13	1	6 years ago	ddk-fpga/330	FPGA HDL Sources.
25	21	0	7 years ago	opensketch/331	simulation and netfpga code
25	2	1	1 year, 3 months ago	icebreaker-candy/332	Eye candy from an iCEBreaker FPGA and a 64×64 LED panel
25	18	0	2 years ago	OV7670-Verilog/333	Verilog modules required to get the OV7670 camera working
25	0	0	6 months ago	gameboy-fpga-cartridge/334	None
24	9	1	3 years ago	ocpi/335	Semi-private RTL development upstream of OpenCPI - this is not the OpenCPI repo!
24	9	0	7 years ago	lsasim/336	Educational load/store instruction set architecture processor simulator
24	18	0	3 years ago	fpga_design/337	这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
24	4	1	1 year, 9 months ago	Lichee-Tang/338	Lichee Tang FPGA board examples
24	5	0	6 years ago	LVDS-7-to-1-Serializer/339	An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
24	20	7	6 years ago	MM/340	Miner Manager
24	11	0	4 years ago	nfmac10g/341	Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
24	4	3	1 year, 3 months ago	v-regex/342	A simple regex library for V
24	4	0	4 months ago	EDN8-PRO/343	EverDrive N8 PRO dev sources
23	6	0	10 months ago	fftdemo/344	A demonstration showing how several components can be compsed to build a simulated spectrogram
23	4	4	7 months ago	A500-8MB-FastRAM/345	8MB FastRAM Board for the Amiga 500 & Amiga 500+
23	7	0	6 years ago	aoOCS/346	The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.
23	17	0	3 years ago	fast/347	FAST
23	4	0	10 months ago	hackaday_supercon_2019_logic_noise_FPGA_workshop/348	Hackaday Supercon 2019 Logic Noise Badge Workshop
23	12	2	4 years ago	FPU/349	IEEE 754 floating point unit in Verilog
23	7	0	8 years ago	aemb/350	Multi-threaded 32-bit embedded core family.
23	11	0	2 years ago	workshops/351	❄️ ? Workshops with Icestudio and the IceZUM Alhambra board
23	4	0	4 months ago	poyo-v/352	Open source RISC-V IP core for FPGA/ASIC design
23	14	0	10 years ago	sparc64soc/353	OpenSPARC-based SoC
23	2	1	a month ago	basic-ecp5-pcb/354	None
23	9	40	3 days ago	mantle/355	mantle library
23	13	0	4 years ago	AES-FPGA/356	AES加密解密算法的Verilog实现
23	15	20	3 years ago	RetroCade_Synth/357	RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.
23	6	2	2 months ago	benchmarks/358	EPFL logic synthesis benchmarks
23	11	0	6 months ago	sha1/359	Verilog implementation of the SHA-1 cryptgraphic hash function
23	8	3	3 years ago	Nitro-Parts-lib-Xilinx/360	This is mainly a simulation library of xilinx primitives that are verilator compatible.
23	10	2	2 years ago	CNN_VGG19_verilog/361	Convolution Neural Network of vgg19 model in verilog
23	7	0	1 year, 4 months ago	Open-FPGA/362	Devotes to open source FPGA
22	10	0	4 years ago	FFT_Verilog/363	FFT implement by verilog_测试验证已通过
22	3	0	1 year, 4 months ago	thunderclap-fpga-arria10/364	Thunderclap hardware for Intel Arria 10 FPGA
22	8	2	1 year, 3 months ago	Posit-HDL-Arithmetic/365	Universal number Posit HDL Arithmetic Architecture generator
22	25	2	1 year, 1 month ago	block-nvdla-sifive/366	None
22	9	0	4 years ago	stx_cookbook/367	Altera Advanced Synthesis Cookbook 11.0
22	19	1	1 year, 6 days ago	LimeSDR-PCIe_GW/368	Altera Cyclone IV FPGA project for the PCIe LimeSDR board
22	7	1	7 months ago	Tang-Nano-examples/369	Tang-Nano-examples
22	12	0	4 years ago	FPGA_Ultrasound/370	CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.
22	12	2	1 year, 11 months ago	ARM9-compatible-soft-CPU-core/371	This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
23	12	0	10 months ago	spi_mem_programmer/372	Small (Q)SPI flash memory programmer in Verilog
22	6	0	10 years ago	osdvu/373	None
22	7	0	2 years ago	Spartan-Mini-NES/374	An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board.
22	3	0	3 days ago	SM3_core/375	None
22	5	0	2 years ago	MIPS-Verilog/376	MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.
22	7	0	8 years ago	tinycpu/377	Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
22	5	1	5 years ago	Y86-CPU/378	A pipeline CPU in Verilog for the Y86 instruction set.
22	29	0	a month ago	jtag_vpi/379	TCP/IP controlled VPI JTAG Interface.
22	9	0	6 months ago	chacha/380	Verilog 2001 implementation of the ChaCha stream cipher.
21	5	0	9 years ago	pdfparser/381	None
21	17	0	3 years ago	99tsp/382	The 99 Traveling Salespeople Project
21	8	0	8 years ago	Pong/383	Pong game on an FPGA in Verilog.
21	4	1	2 years ago	riscv-soc-cores/384	None
21	4	0	2 years ago	bapi-rv32i/385	A extremely size-optimized RV32I soft processor for FPGA.
21	17	4	1 year, 6 months ago	spi-slave/386	SPI Slave for FPGA in Verilog and VHDL
21	13	1	4 months ago	fifo/387	Generic FIFO implementation with optional FWFT
21	15	1	4 years ago	Nitro-Parts-lib-SPI/388	Verilog SPI master and slave
21	13	0	2 years ago	NPU_on_FPGA/389	在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
21	8	7	6 days ago	corescore/390	CoreScore
21	15	0	1 year, 7 months ago	de10nano_vgaHdmi_chip/391	Test for video output using the ADV7513 chip on a de10 nano board
21	20	0	11 months ago	AMBA_AXI_AHB_APB/392	AMBA bus lecture material
21	14	1	2 years ago	nysa-verilog/393	Verilog Repository for GIT
21	3	0	4 months ago	HDMI-to-FPGA-to-APA102-Pixels/394	Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI.
21	9	3	1 year, 5 months ago	ODIN/395	ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
21	0	0	4 months ago	HW-Syn-Lab/396	⚙Hardware Synthesis Laboratory Using Verilog
21	5	2	7 months ago	VGA1306/397	VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!)
21	5	0	7 years ago	usb-de2-fpga/398	Hardware interface for USB controller on DE2 FPGA Platform
21	8	0	a month ago	core_ddr3_controller/399	A DDR3 memory controller in Verilog for various FPGAs
21	0	1	20 days ago	MiSTery/400	Atari ST/STe core for MiST
20	13	0	5 years ago	yafpgatetris/401	Yet Another Tetris on FPGA Implementation
20	4	2	1 year, 9 months ago	recon/402	The RECON project creates library for Nios II Microcontroller System and Tool chain. The library includes a collection of hardware configurations and Arduino-style software APIs.
20	9	1	6 years ago	neural-hardware/403	Verilog library for implementing neural networks.
20	4	1	2 years ago	Verilog-VGA-game/404	A simple game written in Verilog HDL language and display on the VGA screen.
20	22	0	3 years ago	SIMD-architecture/405	Overall multi-core SIMD microarchitecture
20	10	0	23 days ago	Booth_Multipliers/406	Parameterized Booth Multiplier in Verilog 2001
20	2	0	5 years ago	BCOpenMIPS/407	跟着《自己动手写 CPU》书上写的 OpenMIPS CPU。
20	6	0	3 years ago	book-examples/408	None
20	11	1	4 years ago	Propeller_1_Design/409	Propeller 1 design and example files to be run on FPGA boards.
20	8	1	4 years ago	mipscpu/410	Fully pipelined MIPS CPU in Verilog/SystemVerilog with advanced branch prediction, register renaming, and value prediction
20	7	0	9 months ago	Uranus/411	Uranus MIPS processor by MaxXing & USTB NSCSCC team
21	3	1	1 year, 8 months ago	fpga-virtual-graf/412	None
20	9	1	2 years ago	ARM-LEGv8/413	Verilog Implementation of an ARM LEGv8 CPU
20	10	1	3 years ago	Design-and-Verification-of-LDPC-Decoder/414	- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.
20	5	0	1 year, 5 months ago	snes_dejitter/415	NES/SNES 240p de-jitter mod
19	2	0	4 years ago	literate-broccoli/416	An open source FPGA architecture
19	8	0	1 year, 2 months ago	tiny-tpu/417	Small-scale Tensor Processing Unit built on an FPGA
19	10	0	9 years ago	dma_axi/418	AXI DMA 32 / 64 bits
19	7	2	2 years ago	Processor-UVM-Verification/419	System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
19	4	0	1 year, 4 months ago	fpga-examples/420	FPGA examples for 8bitworkshop.com
19	6	0	6 years ago	azpr_cpu/421	用Altera FPGA芯片自制CPU
19	14	2	2 days ago	blake2/422	Hardware implementation of the blake2 hash function
19	2	0	1 year, 29 days ago	A500_ACCEL_RAM_IDE-Rev-2/423	Improved design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
19	2	1	4 years ago	icestick-vga-test/424	Test of ICEstick PLL usage with Yosys/Arachne-PNR/Icetools
19	2	0	a month ago	nintendo-switch-i2s-to-spdif/425	I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal.
19	10	1	2 years ago	up5k-demos/426	ice40 UltraPlus demos
19	5	0	3 years ago	Yoshis-Nightmare/427	FPGA Based Platformer Video Game
19	2	0	4 months ago	EDSAC/428	FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
19	6	0	1 year, 1 month ago	core_audio/429	Audio controller (I2S, SPDIF, DAC)
19	11	1	10 months ago	Open_RegModel/430	?Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
19	7	0	1 year, 6 months ago	verilog-mini-demo/431	Verilog极简教程
18	7	0	2 months ago	RDF-2019/432	DATC RDF
18	5	9	8 years ago	hdl_devel/433	A new CASPER toolflow based on an HDL primitives library
18	1	0	2 years ago	VerilogCommon/434	A repo of basic Verilog/SystemVerilog modules useful in other circuits.
18	8	0	4 years ago	Make-FPGA/435	Repository of Verilog code for Make:FPGA book Chapters 2 & 3.
18	10	0	7 years ago	ovs-hw/436	An open source hardware engine for Open vSwitch on FPGA
18	10	0	3 years ago	usb2_dev/437	USB 2.0 Device IP Core
18	12	2	10 years ago	round_robin_arbiter/438	round robin arbiter
18	4	1	1 year, 11 months ago	Basic-SIMD-Processor-Verilog-Tutorial/439	Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
18	3	0	1 year, 4 months ago	enigmaFPGA/440	Enigma in FPGA
18	2	0	6 months ago	dbgbus/441	A collection of debugging busses developed and presented at zipcpu.com
18	2	0	1 year, 3 months ago	gameduino-fpga-mods/442	Mods of the FPGA code from @jamesbowman's Gameduino file repository
18	0	0	2 years ago	sdaccel_chisel_integration/443	Chisel Project for Integrating RTL code into SDAccel
18	4	0	1 year, 8 months ago	redpid/444	migen + misoc + redpitaya = digital servo
18	10	0	9 months ago	TPU-Tensor-Processing-Unit/445	IC implementation of TPU
18	3	4	6 months ago	amiga_replacement_project/446	This is an attempt to make clean Verilog sources for each chip on the Amiga.
18	9	0	8 months ago	FAST9-Accelerator/447	FAST-9 Accelerator for Corner Detection
18	12	1	8 months ago	matrix-creator-fpga/448	Reference HDL code for the MATRIX Creator's Spartan 6 FPGA
18	6	3	6 months ago	UPduino-v2.1/449	UPduino
18	18	7	4 months ago	UHD-Fairwaves/450	Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.
18	3	0	6 months ago	interpolation/451	Digital Interpolation Techniques Applied to Digital Signal Processing
18	2	1	1 year, 6 months ago	time-sleuth/452	Time Sleuth - Open Source Lag Tester
18	11	0	4 months ago	verilog-arbiter/453	A look ahead, round-robing parametrized arbiter written in Verilog.
18	1	0	2 years ago	UART2NAND/454	Interface for exposing raw NAND i/o over UART to enable pc-side modification.
18	13	1	5 months ago	Pepino/455	None
18	4	0	3 months ago	iverilog-tutorial/456	A quickstart guide on how to use Icarus Verilog.
18	7	1	2 days ago	jtframe/457	Common framework for MiST(er), SiDi, ZX-UNO/DOS and Unamiga core development. With special focus on arcade cores.
18	4	0	5 years ago	Pet2001_Nexys3/458	A Commodore PET in an FPGA.
18	13	1	6 years ago	8051/459	FPGA implementation of the 8051 Microcontroller (Verilog)
17	4	1	2 years ago	UPDuino-OV7670-Camera/460	Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module
17	9	1	2 years ago	FPGA-Accelerator-for-AES-LeNet-VGG16/461	FPGA/AES/LeNet/VGG16
17	3	1	7 months ago	StereoCensus/462	Verilog Implementation of the Census Transform Stereo Vision algorithm
17	13	1	7 years ago	turbo8051/463	turbo 8051
17	3	4	1 year, 11 months ago	fLaCPGA/464	Implementation of fLaC encoder/decoder for FPGA
17	13	0	1 year, 10 months ago	face_detect_open/465	A Voila-Jones face detector hardware implementation
17	9	0	a month ago	xfcp/466	Extensible FPGA control platform
17	3	0	7 years ago	fpgaminer-vanitygen/467	Open Source Bitcoin Vanity Address Generation on FPGAs
17	10	0	3 years ago	SVM-Gaussian-Classification-FPGA/468	SVM Gaussian Classifier of 30x30 greyscale image on Verilog
17	5	0	5 years ago	orgexp/469	Computer Organization Experiment, Shi Qingsong, Zhejiang University.
17	9	0	10 years ago	jpegencode/470	JPEG Encoder Verilog
17	2	0	11 months ago	VirtualTap/471	Mod kit for the Virtual Boy to make it output VGA or RGB video
17	7	1	6 years ago	ws2812-verilog/472	This is a Verilog module to interface with WS2812-based LED strips.
17	12	0	3 years ago	H264/473	H264视频解码verilog实现
17	3	0	2 years ago	USB/474	FPGA USB 1.1 Low-Speed Implementation
17	4	0	8 years ago	amber_samples/475	None
17	12	0	4 months ago	x393_sata/476	mirror of https://git.elphel.com/Elphel/x393_sata
17	9	0	4 years ago	ethernet_10ge_mac_SV_tb/477	SystemVerilog testbench for an Ethernet 10GE MAC core
17	16	0	12 years ago	xge_mac/478	Ethernet 10GE MAC
17	17	1	7 years ago	RSA4096/479	4096bit RSA project, with verilog code, python test code, etc
17	5	0	22 days ago	jelly/480	Original FPGA platform
17	1	0	8 months ago	cisco-hwic-3g-cdma/481	Reverse Engineering of the Cisco HWIC-3G-CDMA PCB
16	4	0	8 years ago	verilog-vga-controller/482	A very simple VGA controller written in verilog
16	1	0	3 years ago	fpga-sram/483	mystorm sram test
16	11	0	6 months ago	sha512/484	Verilog implementation of the SHA-512 hash function.
16	4	0	2 months ago	k1801/485	1801 series ULA reverse engineering
16	10	2	14 years ago	can/486	CAN Protocol Controller
16	7	0	7 years ago	riscv-invicta/487	A simple RISC-V core, described with Verilog
16	12	1	3 years ago	Hardware-Implementation-of-AES-Verilog/488	Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
16	9	12	3 months ago	nanorv32/489	A small 32-bit implementation of the RISC-V architecture
16	1	2	13 days ago	ThymesisFlow/490	Memory Disaggregation on POWER9 with OpenCAPI
16	5	0	4 years ago	icestick/491	Simple demo for Lattice iCEstick board as seen on Hackaday
16	5	5	3 years ago	polaris/492	RISC-V RV64IS-compatible processor for the Kestrel-3
16	3	0	a month ago	core_dvi_framebuffer/493	Minimal DVI / HDMI Framebuffer
16	3	1	a month ago	DetectHumanFaces/494	Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
16	2	0	1 year, 11 months ago	verifla/495	Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
16	3	0	3 years ago	MesaBusProtocol/496	Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
16	9	0	1 year, 6 months ago	riscv_soc/497	Basic RISC-V Test SoC
16	1	0	1 year, 2 months ago	spi_tb/498	CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys
16	4	1	11 days ago	vga-clock/499	None
16	8	0	1 year, 8 months ago	8-bits-RISC-CPU-Verilog/500	Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
16	12	1	3 years ago	fpga-nn/501	NN on FPGA
16	6	0	7 months ago	SIGMA/502	RTL implementation of Flex-DPE.
16	1	0	4 years ago	QuickSilverNEO/503	None
16	5	0	9 months ago	ctfs/504	ctfs write-up
16	0	0	10 months ago	BusPirateUltraHDL/505	Verilog for the Bus Pirate Ultra FPGA
16	13	0	1 year, 7 months ago	gameduino/506	My own version of the @JamesBowman's Gameduino file repository
16	4	0	6 years ago	magukara/507	FPGA-based open-source network tester
16	7	1	10 months ago	ZBC---The-Zero-Board-Computer/508	Based heavily on zet.aluzina.org and Terasic DE0
16	3	0	3 months ago	Fuxi/509	Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
16	4	1	2 months ago	litex_vexriscv_smp/510	Test with LiteX and VexRiscv SMP
16	6	0	a month ago	Simulator_CPU/511	Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog
16	7	1	4 months ago	MacPlus_MiSTer/512	Macintosh Plus for MiSTer
16	5	0	9 years ago	video_stream_scaler/513	Video Stream Scaler
16	11	0	6 months ago	MIPS-Processor/514	5-stage pipelined 32-bit MIPS microprocessor in Verilog
16	12	0	6 years ago	MIPS-Processor-in-Verilog/515	Processor repo
16	2	23	22 days ago	TART/516	Transient Array Radio Telescope
16	13	0	3 years ago	4-way-set-associative-cache-verilog/517	Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
16	9	0	5 years ago	CPU/518	Verilog实现的简单五级流水线CPU，开发平台：Nexys3
16	14	0	1 year, 11 months ago	Open-CryptoNight-ASIC/519	Open source hardware implementation of classic CryptoNight
16	4	7	4 years ago	vector06cc/520	Вектор-06ц в ПЛИС / Vector-06c in FPGA
16	3	0	1 year, 1 month ago	PACoGen/521	PACoGen: Posit Arithmetic Core Generator
16	8	0	2 years ago	SHA256Hasher/522	SHA-256 IP core for ZedBoard (Zynq SoC)
16	3	0	4 years ago	verilog_tutorials_BB/523	verilog tutorials for iCE40HX8K Breakout Board
16	6	0	2 years ago	tinyfpga-bx-game-soc/524	A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games
15	2	0	3 years ago	PitchShifter/525	Change the pitch of your voice in real-time!
15	6	1	3 years ago	arty-glitcher/526	FPGA-based glitcher for the Digilent Arty FPGA development board.
15	11	1	1 year, 9 months ago	zuma-fpga/527	Fine Grain FPGA Overlay Architecture and Tools
15	5	1	4 years ago	mips/528	Mips处理器仿真设计
15	3	0	4 years ago	cpus-pdp8/529	FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source
16	5	0	4 years ago	CoCo3FPGA/530	FPGA implementation of the TRS-80 Color Computer 3 in Verilog, by Gary Becker et al.
15	3	6	6 months ago	icestick-lpc-tpm-sniffer/531	FGBA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit
15	8	0	2 years ago	FFTVisualizer/532	This project demonstrates DSP capabilities of Terasic DE2-115
15	10	0	2 years ago	trainwreck/533	Original RISC-V 1.0 implementation. Not supported.
15	6	0	1 year, 10 months ago	OV7670_NEXYS4_Verilog/534	This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog
15	3	0	10 months ago	tinyfpga_examples/535	Verilog example programs for TinyFPGA
15	1	0	8 months ago	verilog/536	None
15	17	3	3 years ago	Cosmos-OpenSSD/537	None
15	2	0	3 years ago	NeuralHDL/538	None
15	10	0	4 years ago	heterosim/539	HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design space exploration is enabled by a wide range of system configurations. A complete simulation flow with compiler support is provided so that a full system simulation can be performed with various performance metrics returned.
15	6	1	4 years ago	dnn-sim/540	None
15	3	1	6 years ago	descrypt-ztex-bruteforcer/541	descrypt-ztex-bruteforcer
15	5	0	5 months ago	Computer-Experiment-on-the-principle-of-computer-composition/542	杭电计算机学院-《计算机组成原理》上机实验代码工程文件
15	5	1	1 year, 5 months ago	buffets/543	Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
15	10	1	14 days ago	Template_MiSTer/544	Template with latest framework for MiSTer
15	7	0	3 years ago	Centaur/545	Centaur, a framework for hybrid CPU-FPGA databases
15	7	0	2 years ago	posture_recognition_CNN/546	To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface.
16	1	0	a month ago	UltraMIPS_NSCSCC/547	UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
15	12	2	5 years ago	CAN-Bus-Controller/548	An CAN bus Controller implemented in Verilog
15	5	0	8 years ago	openmsp430/549	openMSP430 CPU core (from OpenCores)
15	9	0	3 years ago	Curso-Electronica-Digital-para-makers-con-FPGAs-Libres/550	Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers
15	5	0	5 years ago	fpga-spartan6/551	Support for zScale on Spartan6 FPGAs
15	2	0	5 months ago	ws2812-core/552	verilog core for ws2812 leds
14	12	0	2 years ago	verilog-osx/553	Barerbones OSX based Verilog simulation toolchain.
14	1	0	9 years ago	Oberwolfach-explorations/554	collaboration on work in progress
14	1	0	6 months ago	DSP-RTL-Lib/555	RTL Verilog library for various DSP modules
14	4	1	3 years ago	handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/556	None
14	1	0	2 years ago	UPduino-Mecrisp-Ice-15kB/557	Mecrisp-Ice Forth running on 16bit j1a processor (iCE40UP5k based UPduino board) with full 15kB of bram and 48bit Floating Point Library.
14	0	0	2 years ago	iPxs-Text/558	Text for a iPxs-Collection.
14	3	1	3 years ago	Menu_MIST/559	Dummy FPGA core to display menu at startup
14	9	0	9 years ago	dma_ahb/560	AHB DMA 32 / 64 bits
14	5	0	3 years ago	iir-bandstop-filter/561	Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
14	22	1	2 years ago	moneroasic/562	Cryptonight Monero Verilog code for ASIC
14	2	0	5 years ago	WitnessProtection/563	in FPGA
14	1	0	10 months ago	RePLIA/564	FPGA Based lock in amplifier
14	12	4	a month ago	ZX-Spectrum_MISTer/565	None
14	4	0	10 days ago	SiDi-FPGA/566	SiDi FPGA for retro systems.
14	3	2	4 years ago	icestickPWM/567	Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo)
14	1	0	3 months ago	EI332/568	SJTU EI332 CPU完整实验代码及报告
14	2	0	26 days ago	serv_soc/569	SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
14	10	0	5 months ago	DA_PUF_Library/570	Defense/Attack PUF Library (DA PUF Library)
14	1	0	8 months ago	Async-Karin/571	Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
14	5	1	2 years ago	anlogic-picorv32/572	Optimized picorv32 core for anlogic FPGA
14	9	0	3 years ago	ee260_lab/573	EE 260 Winter 2017: Advanced VLSI Design
14	3	0	1 year, 4 months ago	wb_intercon/574	Wishbone interconnect utilities
14	10	1	10 years ago	dvb_s2_ldpc_decoder/575	DVB-S2 LDPC Decoder
14	13	0	1 year, 1 month ago	FPGA_CryptoNight_V7/576	FPGA CryptoNight V7 Minner
14	2	1	2 months ago	icozip/577	A ZipCPU demonstration port for the icoboard
14	8	1	5 years ago	AHB_Bus_Matrix/578	None
14	6	2	4 years ago	idea/579	iDEA FPGA Soft Processor
14	7	0	11 months ago	nica/580	An infrastructure for inline acceleration of network applications
14	5	1	7 months ago	SDR-Micron/581	SDR Micron USB receiver
14	1	0	3 years ago	iCEstick-hacks/582	iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
14	3	1	1 year, 1 month ago	TMR/583	Triple Modular Redundancy
14	12	0	19 hours ago	apio-examples/584	? Apio examples
14	8	1	1 year, 6 months ago	Zeus/585	NVDLA small config implementation on Zynq ZCU104 (evaluation)
14	5	0	6 years ago	FPGA_Stereo_Depth_Map/586	None
14	15	1	8 years ago	MIPS-in-Verilog/587	An implementation of MIPS single cycle datapath in Verilog.
14	1	1	1 year, 2 months ago	Electronic-competition/588	全国大学生电子设计大赛往年赛题--仪器仪表类练习
14	4	4	3 months ago	MiSTer-Arcade-SEGASYS1/589	FPGA implementation of SEGA SYSTEM 1 arcade board
14	4	0	5 months ago	bitcoin_mining/590	Simple test fpga bitcoin miner
14	7	0	1 year, 8 months ago	RISC-Processor/591	32-bit RISC processor
14	4	0	1 year, 6 months ago	arrowzip/592	A ZipCPU based demonstration of the MAX1000 FPGA board
14	1	0	2 years ago	arty-videocap/593	Repeat and capture the video signal with Digilent Arty-A7 and a video extender board.
14	5	0	9 months ago	Digital_Front_End_Verilog/594	None
14	4	0	7 days ago	avr/595	Reads a state transition system and performs property checking
14	1	1	6 years ago	ethpipe/596	EtherPIPE: an Ethernet character device for packet processing
14	1	0	1 year, 2 months ago	Merlin/597	RISC-V RV32I[C] CPU (Apache-2.0) - Merlin
15	2	0	3 years ago	RiverRaidFPGA/598	River Raid game on FPGA
13	2	1	11 months ago	galaksija/599	Galaksija computer for FPGA
13	10	0	8 months ago	matrix-voice-fpga/600	HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one
13	0	0	10 months ago	FPGAGameBoy/601	an implementation of the GameBoy in Verilog
13	2	1	2 years ago	mikrobus-upduino/602	Dual MikroBUS board for Upduino 2 FPGA
13	8	0	1 year, 11 months ago	wb_sdram_ctrl/603	SDRAM controller with multiple wishbone slave ports
13	19	2	2 years ago	FPGA-Keccak-Miner/604	None
13	0	0	1 year, 11 months ago	fpga_tv/605	Some crazy experiments about using a FPGA to transmit a TV signal old-style
13	4	0	5 years ago	ShootingGame-FPGA/606	Using verilog-HDL, xilinx-ISE and nexys-iii. A shooting game based on VGA and ps/2 keyboard.
13	3	0	4 years ago	ASIC-FPGA-tetris/607	a FPGA implementation for tetris game.
13	4	1	4 years ago	dyract/608	DyRACT Open Source Repository
13	5	1	3 years ago	Verilog_Calculator_Matrix_Multiplication/609	This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
13	12	0	7 years ago	ASIC/610	EE 287 2012 Fall
13	9	0	1 year, 2 months ago	Ethernet-design-verilog/611	Gigabit Ethernet UDP communication driver
13	6	0	4 months ago	MemTest_MiSTer/612	None
13	1	0	1 year, 26 days ago	systolic-array-matrix-multiplier/613	A systolic array matrix multiplier
14	7	0	4 years ago	ring_network-based-multicore-/614	多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
13	2	0	2 years ago	Ada-PicoRV32-example/615	Example of Ada code running on the PicoRV32 RISC-V CPU for FPGA
13	3	1	a day ago	cpc_ram_expansion/616	A series of Amstrad CPC PCBs including a backplane, ROM and 512K and 1MByte RAM expansions.
13	3	0	4 years ago	FPGA/617	computer hardware system including ps2/vga with tank war game in verilog and mips
13	4	4	6 days ago	VossII/618	The source code to the Voss II Hardware Verification Suite
13	5	0	1 year, 8 months ago	openzcore/619	powerpc processor prototype and an example of semiconductor startup biz plan
13	0	0	3 years ago	8bit-computer/620	Simple 8-bit computer build in Verilog
13	9	4	5 months ago	Arcade-GnG_MiSTer/621	Arcade Ghosts'n Goblins for MiSTer
13	7	2	1 year, 8 months ago	Parser-Verilog/622	A Standalone Structural Verilog Parser
13	0	0	11 months ago	risc-v/623	RISC-VのCPU作った
13	4	7	3 years ago	liquid-router/624	The Subutai™ Router open hardware project sources.
13	4	4	1 year, 10 days ago	yosys-bench/625	Benchmarks for Yosys development
13	2	1	10 years ago	soc-lm32/626	Open source/hardware SoC plattform based on the lattice mico 32 softcore
13	2	0	5 months ago	Nu6509/627	Emulate a 6509 with a 6502
13	0	0	10 months ago	wbfmtx/628	A wishbone controlled FM transmitter hack
13	0	0	a month ago	ics-adpcm/629	Programmable multichannel ADPCM decoder for FPGA
13	10	12	2 months ago	sancus-core/630	Minimal OpenMSP430 hardware extensions for isolation and attestation
13	1	0	3 years ago	fpga_csgo/631	Counter Strike: Global Offensive FPGA Version (LOL)
13	2	0	3 years ago	computer-systems-ucas/632	中国科学院大学计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
13	9	0	1 year, 28 days ago	computer-organization-lab/633	中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
13	23	0	2 years ago	sata3_host_controller/634	It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
13	5	3	1 year, 4 months ago	s7_mini_fpga/635	Example designs for the Spartan7 "S7 Mini" FPGA board
13	6	0	1 year, 11 months ago	vp_awsfpga/636	Virtual Platform for AWS FPGA support
13	2	1	9 months ago	SNKVerilog/637	Verilog definitions of custom SNK chips, for repairs and preservation.
13	9	1	6 years ago	i2s/638	i2s core, with support for both transmit and receive
13	11	1	4 years ago	lisnoc/639	LIS Network-on-Chip Implementation
13	1	5	28 days ago	circuitgraph/640	Tools for working with circuits as graphs in python
13	3	1	2 years ago	Nexys-4-DDR-Ethernet-Mac/641	Ethernet MAC for the Digilent Nexys 4 DDR FPGA.
13	6	0	5 years ago	NetFPGA-10G-UPB-OpenFlow/642	An OpenFlow implementation for the NetFPGA-10G card
13	4	0	11 months ago	SparkRoad-FPGA/643	None
13	0	0	3 days ago	Colorlight-FPGA-Projects/644	current focus on Colorlight i5-v6.0
13	3	0	4 months ago	riscv_sbc/645	A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
13	15	0	5 years ago	Open-Source-Network-on-Chip-Router-RTL/646	None
13	6	0	3 months ago	evoapproxlib/647	Library of approximate arithmetic circuits
13	13	0	2 years ago	Examples-in-book-write-your-own-cpu/648	《自己动手写CPU》一书附带的文件
13	10	0	1 year, 20 days ago	gemac/649	Gigabit MAC + UDP/TCP/IP offload Engine
12	3	0	2 years ago	ipxactexamplelib/650	Contains examples to start with Kactus2.
12	0	0	8 months ago	eecs151/651	http://inst.eecs.berkeley.edu/~eecs151/fa19/
12	3	0	7 years ago	80211scrambler/652	Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.
12	7	7	3 years ago	pars/653	None
12	2	0	4 months ago	FPGA_DevKit_HX1006A/654	None
12	12	4	3 years ago	DE1-SoC-Sound/655	None
12	0	2	2 months ago	Deep-DarkFantasy/656	Global Dark Mode for ALL apps on ANY platforms.
12	6	0	4 years ago	PCIE_AXI_BRIDGE/657	Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
12	1	0	2 months ago	jtopl/658	Verilog module compatible with Yamaha OPL chips
12	3	2	4 years ago	hardcaml-riscv/659	RISC-V instruction set CPUs in HardCaml
12	5	0	5 years ago	mips32r1_core/660	A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.
12	2	0	1 year, 11 months ago	pinky8bitcpu/661	Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3
12	5	2	6 years ago	Modular-Exponentiation/662	Verilog Implementation of modular exponentiation using Montgomery multiplication
12	7	0	2 years ago	JPEG-Decoder/663	Verilog Code for a JPEG Decoder
12	6	0	3 months ago	fpga-bpf/664	A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark
12	8	0	2 years ago	CPU/665	CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
11	13	1	1 year, 5 months ago	OpenHPSDR-Firmware/666	This is the verilog code for the various FPGA in the OpenHPSDR Radios
12	10	0	3 years ago	FreeAHB/667	AHB Master
12	2	0	1 year, 5 months ago	CNN-Based-FPGA/668	CNN implementation based FPGA
12	1	3	3 years ago	oram/669	Hardware implementation of ORAM
12	1	0	6 years ago	milkymist-mmu/670	Milkymist MMU project
12	5	1	6 months ago	Vision-FPGA-SoM/671	tinyVision.ai Vision & Sensor FPGA System on Module
12	3	0	1 year, 10 months ago	Flappy-Bird/672	FPGA program :VGA-GAME
12	12	0	6 years ago	logi-pong-chu-examples/673	example code for the logi-boards from pong chu HDL book
12	5	0	5 years ago	nes_mappers/674	NES mappers
12	4	0	1 year, 4 months ago	Verilog-FIR/675	FIR implemention with Verilog
12	3	0	10 months ago	64-bit-Universal-Floating-Point-ISA-Compute-Engine/676	RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
12	13	4	3 years ago	test_jpeg/677	This is a myhdl test environment for the open-cores jpeg_encoder.
12	0	1	1 year, 5 months ago	HDL-deflate/678	FPGA implementation of deflate (de)compress RFC 1950/1951
12	0	0	4 years ago	yosys-ice-experiments/679	Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain
12	3	1	5 years ago	ICEd/680	Open Hardware for Open Source FPGA Toolchain
12	12	1	1 year, 10 months ago	FPGA_rtime_HDR_video/681	We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
12	5	0	2 years ago	Autonomous-Drone-Design/682	Design real-time image processing, object recognition and PID control for Autonomous Drone.
12	4	0	5 years ago	radio-86rk-wxeda/683	Port of the original radio-86rk_SDRAM Altera DE1 code to the WXEDA board
12	9	1	2 years ago	c64-dodgypla/684	Commodore 64 PLA replacement
12	5	0	8 years ago	Open-Source-System-on-Chip-Experiment/685	Just experimenting with Open Source SoCs on my Altera dev kit.
12	3	0	2 years ago	crap-o-scope/686	crap-o-scope scope implementation for icestick
12	1	0	4 years ago	consolite-hardware/687	A hardware implementation of the Consolite game console written in Verilog.
12	0	0	2 years ago	RISCV-CPU/688	SJTU Computer Architecture(1) Hw
12	1	0	2 months ago	3DORGB/689	RGB Project for most 3DO consoles.
12	2	0	8 months ago	OPDB/690	OpenPiton Design Benchmark
12	4	0	8 years ago	orpsoc/691	[abandoned fork] OpenRISC Reference Platform SoC
12	4	1	a month ago	jtdd/692	Double Dragon FPGA core
12	8	0	7 years ago	VP2motion/693	FPGA based motion controller for RepRap style 3D printers
12	6	0	4 months ago	Reindeer_Step/694	Reindeer Soft CPU for Step CYC10 FPGA board
12	3	0	2 years ago	DSITx/695	FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display
12	6	2	5 years ago	Pano-Logic-Zero-Client-G2-FPGA-Demo/696	Constraints file and Verilog demo code for the Pano Logic Zero Client G2
12	7	0	3 years ago	mriscv_vivado/697	A 32-bit Microcontroller for NEXYS4-DDR fpga based on mriscv.
12	2	2	11 months ago	upduino/698	None
12	8	0	4 years ago	2-way-Set-Associative-Cache-Controller/699	Synthesizable and Parameterized Cache Controller in Verilog
12	6	0	2 years ago	FPGA-SM3-HASH/700	Description of Chinese SM3 Hash algorithm with Verilog HDL
12	1	0	6 years ago	nand2tetris-vhdl/701	nand2tetris files converted to VHDL so I can simulate them on an FPGA
11	13	0	1 year, 27 days ago	fpga-sdk-prj/702	FPGA-based SDK projects for SCRx cores
11	0	1	a month ago	TurboMaster/703	Reverse Engineering of the Schnedler Systems 4MHz TurboMaster accelerator cartridge for the Commodore 64
11	8	0	8 years ago	wimax_ofdm/704	Partial Verilog implimentation of a WiMAX OFDM Phy
11	5	1	1 year, 2 months ago	HDL-Bits-Solutions/705	This is a repository containing solutions to the problem statements given in HDL Bits website.
11	5	0	5 years ago	parallella-fpga-tutorials/706	A place to store the code for FPGA tutorial projects I have written for the Parallella [http://parallellagram.org]
11	1	0	9 months ago	bitmips2019/707	None
11	2	0	1 year, 7 months ago	hilotof/708	HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs
11	0	1	2 years ago	miniatom/709	Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard
11	0	0	4 months ago	MiSTer-Arcade-DigDug/710	FPGA implementation of DigDug arcade game
11	0	0	2 years ago	mera400f/711	MERA-400 in an FPGA
11	3	0	9 years ago	opengg/712	OpenGL-like graphics pipeline on a Xilinx FPGA
11	1	1	1 year, 3 months ago	Conways-Game-of-Life-with-Vlang/713	Conway's life game in V
11	8	0	2 years ago	fpga-hdl/714	A set of small Verilog projects, to simulate and implement on FPGA development boards
11	4	0	4 years ago	Hardware_circular_buffer_controller/715	This is a circular buffer controller used in FPGA.
11	7	0	8 years ago	Verilog-Pac-Man/716	Verilog implementation of Pac-Man made for a class's final project
11	10	0	7 years ago	4way-cache/717	Verilog cache implementation of 4-way FIFO 16k Cache
11	7	0	3 years ago	TinyFPGA-SoC/718	Opensource building blocks for TinyFPGA microcontrollers and retro computers.
11	2	0	1 year, 9 months ago	xulalx25soc/719	A System on a Chip Implementation for the XuLA2-LX25 board
11	12	0	2 years ago	OFDM_802_11/720	None
11	3	0	7 years ago	ov/721	None
11	5	0	2 years ago	pciebench-netfpga/722	pcie-bench code for NetFPGA/VCU709 cards
11	9	1	8 years ago	mips_16/723	Educational 16-bit MIPS Processor
11	3	0	4 months ago	Tutorials_MiSTer/724	Tutorials from the mist project converted to MiSTer
11	3	0	a month ago	ssith-aws-fpga/725	Host software for running SSITH processors on AWS F1 FPGAs
11	3	3	6 years ago	ahci_mpi/726	an sata controller using smallest resource.
11	12	1	1 year, 9 months ago	digital-design-lab-manual/727	Digital Design Labs
11	5	0	2 months ago	Fixed-Floating-Point-Adder-Multiplier/728	16-bit Adder Multiplier hardware on Digilent Basys 3
11	11	5	3 years ago	papiGB/729	Game Boy Classic fully functional FPGA implementation from scratch
11	1	0	2 months ago	de10-nano-riscv/730	A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
11	9	1	4 years ago	BD3_FPGA/731	新一代北斗卫星导航监测接收机的FPGA实现
11	11	0	1 year, 8 months ago	vivado-ip-cores/732	IP Cores that can be used within Vivado
11	2	0	9 months ago	bfcpu/733	A simple CPU that runs Br*nfck code.
11	4	0	1 year, 11 months ago	digital-design/734	An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
11	3	0	1 year, 1 month ago	cdsAsync/735	cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
11	1	0	9 months ago	ZC-RISCV-CORE/736	ZC RISCV CORE
10	0	0	5 months ago	oberon/737	None
11	9	0	6 years ago	Verilog-I2C-Slave/738	Verilog I2C Slave
11	5	0	4 years ago	gng/739	Gaussian noise generator Verilog IP core
11	6	1	8 years ago	md5_core/740	MD5 core in verilog
11	5	0	7 years ago	orbuild/741	OpenRISC build system
11	4	0	3 years ago	OpenMIPS/742	OpenMIPS——《自己动手写CPU》处理器部分
11	7	0	1 year, 9 months ago	Convolution-using-systolic-arrays/743	None
11	0	0	1 year, 10 months ago	ulx3s-foss-blinky/744	A template project for the ULX3S ECP5 FPGA board using only Open Source Software
11	2	0	1 year, 1 month ago	yoloRISC/745	A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
11	0	0	5 months ago	Life_MiSTer/746	Conway's Game of Life in FPGA
11	3	0	3 months ago	picorv32_Xilinx/747	A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
11	6	0	3 years ago	ice40-stm32-sdram/748	Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA
11	3	1	4 years ago	n64rgb/749	Alternative configuration for CPLD style N64 RGB mods to produce crisper image in 240p/288p modes
11	2	0	1 year, 25 days ago	net2axis/750	Verilog network module. Models network traffic from pcap to AXI-Stream
11	13	0	8 years ago	axi-bfm/751	git clone of http://code.google.com/p/axi-bfm/
11	0	2	6 months ago	plaid-bib-cpld/752	A replica of the Ad Lib MCA sound card, now with a CPLD instead of the bus interface chip
11	2	0	3 years ago	fpga-synth/753	FPGA based modular synth.
11	4	0	1 year, 3 months ago	arm_vhdl/754	Portable FPGA project based on the ARM DesignStart bundle with ARM Cortex-M3 processor
11	11	0	2 years ago	riscvv/755	an open source uvm verification platform for e200 (riscv)
11	1	0	2 years ago	mips-cpu/756	The Verilog implementation of five-stage-pipelined MIPS CPU (Classic RISC pipeline)
11	7	0	1 year, 7 months ago	FPGA_NTP_SERVER/757	None
11	1	0	2 years ago	sky-machine/758	An untyped lambda calculus machine designed in FPGA.
11	8	0	2 days ago	sha3/759	FIPS 202 compliant SHA-3 core in Verilog
11	0	0	5 years ago	tetris-verilog/760	Verilog Tetris
11	1	0	1 year, 2 months ago	100DayFPGA/761	Scratchpad repository for the 100-day FPGA challenge
11	5	0	5 years ago	md5cracker/762	A Hardware MD5 Cracker for the Cyclone V SoC
11	0	0	3 years ago	brainf__k_CPU/763	A CPU that executes brainf**k language. Can be synthesized on FPGA
11	9	1	1 year, 8 months ago	fpga-tutorial/764	FPGA tutorial
11	2	0	3 years ago	Hardware-Accelerated-SNN/765	Architecture for Spiking Neural Network
11	1	0	5 months ago	CPU_start_from_0/766	从零开始设计一个CPU (Verilog)
10	11	17	8 years ago	G729_CODE/767	G.729 Encoder
10	7	0	5 years ago	mor1kx-dev-env/768	Development and verification environment for the mor1kx core
10	1	0	6 months ago	Arduboy_MiSTer/769	Arduboy core for MiSTer, ported by Dan O'Shea and now based on Iulian Gheorghiu's atmega core.
10	10	0	4 years ago	Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM/770	Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
10	3	2	5 years ago	novena-afe-hs-fpga/771	High Speed Analog Front End FPGA Firmware for Novena PVT1
10	4	1	7 months ago	tonic/772	A Programmable Hardware Architecture for Network Transport Logic
10	2	0	8 months ago	max2-audio-dac/773	24-bit Stereo Audio DAC for Raspberry Pi
10	3	0	3 years ago	Fpga-PM-Radio/774	Implement Phase Modulation Radio Transmitter in FPGA Altera MAX10, with Marsohod3bis FPGA board.
10	0	0	1 year, 9 months ago	ice-risc/775	RISC CPU by Icenowy
10	2	0	a month ago	zxuno_spectrum_core/776	A ZX Spectrum hardware description for the ZXUNO hardware and other platforms
10	6	0	3 years ago	energy_detection_system/777	USRP-N210 mixed FPGA/software implementation of an automated spectrum scanner
10	0	0	10 years ago	qs-avg/778	Proofs of Quicksort's average case complexity
10	3	0	7 years ago	Midi_SynthFpga/779	Sound synthetizer with an fpga
10	1	0	7 months ago	Jaguar_MiSTer_new/780	None
10	2	0	2 years ago	bladerf-dvbs2/781	16-APSK DVB-S2 Transmitter for BladeRF
10	2	0	6 years ago	parallel-processor-design/782	Super scalar Processor design
10	6	1	7 years ago	mojo-miner/783	A bitcoin miner for the mojo fpga development board by embedded micro
10	2	2	2 years ago	protohdl/784	Streaming FPGA/ASIC code generator for Google Protocol Buffers.
10	1	0	25 days ago	Solutions-to-HDLbits-Verilog-sets/785	Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
10	1	0	2 years ago	pipelined-mips/786	A Verilog implementation of a pipelined MIPS processor
10	4	0	2 years ago	LeNet_RTL/787	An LeNet RTL implement onto FPGA
10	6	0	4 years ago	Example-Codes-for-Snorkeling-in-Verilog-Bay/788	Example Codes for Snorkeling in Verilog Bay
10	4	0	24 days ago	vsdmixedsignalflow/789	This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.
10	3	0	1 year, 6 months ago	BK0011M_MIST/790	BK0011M (USSR retro home computer) core for MiST board
10	5	0	4 years ago	verilog-tetris/791	A Verilog implementation of the popular video game Tetris.
10	0	0	1 year, 7 months ago	Virtual-Console/792	work in progress of a xterm-256color terminal
10	3	0	5 years ago	SIMPLE_MIPS_CPU/793	A simple MIPS CPU, for fun.
10	2	1	4 months ago	rudolv/794	RISC-V processor
10	4	0	5 years ago	Computer-Architecture/795	A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
10	4	0	4 years ago	NCL_sandbox/796	Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determined design in a familiar context. The tools used are Icarus verilog and gtkwave.
10	2	0	4 years ago	hunter-fan-controller/797	An Lattice iCE40 FPGA based controller for ceiling fans by the Hunter Fan Company
10	7	0	2 years ago	Mustang/798	Top level of PulseRain M10 RTL design
10	3	0	5 months ago	00_Image_Rotate/799	视频旋转（2019FPGA大赛）
10	1	0	9 months ago	panog1_opl3/800	A port of the OPL3 to the Panologic G1 thin client
10	1	1	3 years ago	fpga-cam-spartan6-mt9v034/801	None
10	2	17	1 year, 4 months ago	Verilog/802	None
10	0	0	3 years ago	fpga_nes/803	Recreating an NES in verilog
10	8	1	3 years ago	Radix-2-FFT/804	Verilog code for a circuit implementation of Radix-2 FFT
10	9	0	4 years ago	Asynchronous-FIFO/805	Asynchronous fifo in verilog
10	3	0	5 years ago	SuperHexagonFPGA/806	FPGA clone of the game Super Hexagon
10	0	0	4 months ago	DVP_to_UDP/807	Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA
10	4	0	a month ago	uart/808	A simple implementation of a UART modem in Verilog.
10	4	1	3 years ago	fpga-wpa-psk-bruteforcer/809	WPA-PSK cracking for FPGA devices
10	2	0	2 years ago	bextdep/810	Reference Hardware Implementations of Bit Extract/Deposit Instructions
10	8	0	5 years ago	FT245_interface/811	Verilog module to communicate with the FT245 interface of an FTDI FT2232H
10	4	1	4 years ago	dvi_lvds/812	DVI to LVDS Verilog converter
10	1	4	8 months ago	fluent10g/813	Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
10	3	0	9 years ago	crunchy/814	Distributed FPGA Number Crunching for the Masses
10	4	0	4 years ago	ConvNN_FPGA_Accelerator/815	None
10	1	0	8 years ago	bfcpu2/816	A pipelined brainfuck softcore in Verilog
10	1	0	5 years ago	v.vga.font8x16/817	Verilog VGA font generator 8 by 16 pixels
10	5	0	3 years ago	Single-Cycle-CPU/818	None
10	9	0	15 years ago	uart16550/819	UART 16550 core
10	2	1	10 months ago	RISC-V-CPU/820	A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
10	0	0	2 months ago	ulx3s_examples/821	Example Verilog code for Ulx3s
10	10	0	2 years ago	32-bit-MIPS-Processor/822	A 32-bit MIPS processor used Altera Quartus II with Verilog.
10	2	0	8 months ago	color3/823	Information about eeColor Color3 HDMI FPGA board
10	2	0	9 years ago	oc-i2c/824	I2C controller core from Opencores.org
10	1	4	1 year, 2 months ago	pumpkin/825	None
10	5	0	5 years ago	numatolib/826	Demo Library for Numato FPGA Boards
10	0	0	2 months ago	fomu-vga/827	None
10	9	2	2 years ago	Verilog-Snippets/828	Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani
10	2	0	5 years ago	mc6502/829	Cycle accurate MC6502 compatible processor in Verilog.
10	1	0	6 years ago	next186_soc_pc/830	Next186 SoC PC
10	0	0	5 years ago	JagNetlists/831	Atari Jaguar netlists compiler
10	1	0	9 months ago	ice40_8bitworkshop/832	"Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board.
10	8	0	3 years ago	ft232h-core/833	None
10	7	0	10 months ago	digital_lab/834	Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty
10	9	0	2 years ago	nitro-parts-lib-mipi/835	RTL for mipi serialize and deserialize
10	1	0	6 months ago	wbpmic/836	Wishbone controller for a MEMs microphone
10	2	0	17 days ago	composite-design/837	仪科综合电子设计
9	1	0	9 years ago	Four-Color-Theorem-Maintenance/838	Fixed FCT proof for latest coq and ssreflect
9	1	0	1 year, 6 months ago	MIPS-pipeline-CPU/839	None
9	4	0	3 years ago	dst40/840	None
9	0	0	9 months ago	Arduissimo/841	Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
9	2	0	1 year, 6 months ago	FPGA_Vending_Machine/842	东南大学信息学院大三短学期FPGA课程设计——售货机
9	0	0	3 months ago	HPS2FPGAmapping/843	SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
9	22	2	5 days ago	iob-soc/844	RISC-V System on Chip Template Based on the picorv32 Processor
9	1	0	11 months ago	fpga_image_processing/845	IP operations in verilog (simulation and implementation on ice40)
9	8	4	a month ago	Archie_MiSTer/846	Acorn Archimedes for MiSTer
9	2	0	5 years ago	UART_ECHO/847	Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.
9	3	2	3 years ago	vivado-picorv32/848	A Vivado IP package of the PicoRV32 RISC-V processor
9	4	0	3 years ago	S64X7/849	64-bit MISC Architecture CPU
9	2	0	5 years ago	uart/850	Verilog uart receiver and transmitter modules for De0 Nano
9	5	0	5 years ago	bwa-mem-sw/851	None
9	8	0	2 years ago	single-cycle-CPU/852	单周期CPU设计与实现
9	1	0	4 months ago	Colorlight-5A-75B/853	Notes for Colorlight-5A-75B.
9	4	0	12 years ago	verilog_cordic_core/854	configurable cordic core in verilog
9	1	0	7 years ago	ethernet_dpi/855	DPI module for Ethernet-based interaction with Verilator simulations
9	1	0	6 years ago	Gameboy/856	18-545 Fighting Meerkats
9	0	1	10 years ago	Amigo/857	Amigo 1000 - Conversion of the Amiga 1000 schematic into Verilog 2001 RTL
9	4	0	2 months ago	FPGA-Snappy-Decompressor/858	A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
9	5	1	2 years ago	FPGA-edge_detect/859	Nexys 4 DDR Artix-7
9	2	0	2 years ago	workshop_badge/860	Proposal for FPGA workshop badge for Hackaday Belgrade 2018
9	6	0	1 year, 4 months ago	AD9361_TX_MSK/861	A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
9	4	0	3 years ago	hdmi-ts/862	hdmi-ts Project
9	1	0	2 years ago	cmpe220fall16/863	Public repository of the UCSC CMPE220 class project
9	3	0	3 years ago	FPGAMAG18/864	FPGA Magazine No.18 - RISC-V
9	3	0	1 year, 11 months ago	BareBonesCortexM0/865	Extremely basic CortexM0 SoC based on ARM DesignStart Eval
9	1	0	1 year, 2 months ago	sequent/866	Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog
9	5	0	1 year, 8 months ago	Computer-Organization-and-Architecture-LAB/867	Solution to COA LAB Assgn, IIT Kharagpur
9	8	0	5 months ago	DDLM/868	Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
9	4	0	8 months ago	Arcade-1943_MiSTer/869	CAPCOM's 1943 arcade clone. (port of JT1943 core)
9	3	5	5 years ago	bk0010/870	БК - в ФПГА!
9	6	0	2 years ago	bbcpu/871	None
9	10	1	3 years ago	sobel/872	Implementation of Sobel Filter in Verilog
9	3	0	2 years ago	Nexys-4-DDR-Keyboard/873	None
9	4	0	1 year, 9 months ago	tinyzip/874	A ZipCPU based demonstration for the TinyFPGA BX board
9	0	0	10 days ago	Verilog-Playground/875	Verilog Experiment Area
9	2	0	2 days ago	spam-1/876	Simple CPU simulation built using Logism Evolution and including and Assembler build using google sheets
9	2	1	12 hours ago	Silice-Playground/877	None
9	4	0	16 years ago	jtag/878	JTAG Test Access Port (TAP)
9	3	0	8 months ago	rtcclock/879	A Real Time Clock core for FPGA's
9	1	0	3 years ago	ice40-toys-and-examples/880	Some toy stuff I made while learning Verilog/FPGAs/Ice40 Toolchain
9	1	0	5 years ago	VerilogCogs/881	Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
9	179	0	4 years ago	ece4750-tut4-verilog/882	ECE 4750 Tutorial 4: Verilog Hardware Description Language
9	3	8	1 year, 11 months ago	automatic-chainsaw/883	A custom 16-bit computer
9	3	0	1 year, 8 months ago	MIPS-V/884	组成原理课程实验：MIPS 流水线CPU，实现36条指令，转发，冒险检测
9	1	0	3 years ago	XNORNet4FPGA/885	XNOR-Net inference on low-power IGLOO FPGA using Chisel
9	2	0	2 years ago	stargate/886	StarGate is a programming and runtime framework for enabing easy and efficient deployment of various accerators.
9	2	0	5 years ago	Single-Cycle-MIPS/887	Single Cycle MIPS Implementation in Verilog
9	0	1	5 years ago	oram/888	Recursive unified ORAM
9	7	6	4 years ago	pifo-hardware/889	None
9	3	0	1 year, 2 months ago	HDLBits_Practice_verilog/890	This is a practice of verilog coding
9	0	0	4 years ago	VerilogTIS100/891	Implementation of the TIS-100 Tessellated Intelligence System.
9	5	0	21 days ago	M65C02A/892	Enhanced 6502/65C02 Microprogrammed Verilog Processor Core
9	1	1	1 year, 11 months ago	32-bit-Multicycle-CPU/893	Verilog Implementation of a 32-bit Multicycle CPU
9	3	0	4 years ago	NetUP_Dual_Universal_CI-fpga/894	VHDL NetUP Universal Dual DVB-CI FPGA firmware
9	9	0	8 years ago	netv_fpga_hdmi_overlay/895	Mirror of NeTV FPGA Verilog Code
9	2	0	7 months ago	ulx3s_zx81/896	ZX80/81 implementation for the Ulx3s
9	3	0	2 years ago	xdcom/897	This is a demo for still image compression application
9	7	0	a month ago	general-cores/898	general-cores
9	6	0	3 years ago	HDC-Language-Recognition/899	Hyperdimensional computing for language recognition: Matlab and RTL implementations
9	2	1	10 months ago	verilog/900	Verilog Examples and WebFPGA Standard Library
9	3	2	2 years ago	TDC/901	Verilog implementation of a tapped delay line TDC
9	9	0	3 years ago	AXI_BFM/902	AXI4 BFM in Verilog
9	7	1	6 years ago	apbi2c/903	APB to I2C
9	1	0	1 year, 11 months ago	VerilogSHA256Miner/904	Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.
9	7	1	2 years ago	AX301/905	AX301
9	11	0	1 year, 11 months ago	CurriculumDesign-PrinciplesOfComputerOrganization/906	华中科技大学计算机15级计算机组成原理课程设计，分别用logisim和Verilog实现简单CPU
9	0	0	6 years ago	all_spark_cube/907	All files related to the All Spark Cube built by Adaptive Computing and friends
9	5	0	7 years ago	verilog-pong/908	Pong on an FPGA in Verilog.
9	5	0	4 years ago	FPGA_FM_transmitter/909	Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.
9	4	0	3 years ago	A2/910	None
9	4	0	7 years ago	xula-lib-verilog/911	Collection of helper modules for XuLA-200 FPGA development board written in Verilog-2001.
9	1	0	2 years ago	curso-verilog.v/912	None
9	4	0	1 year, 10 months ago	MIPS-Architecture-CPU-design/913	BUAA SCSE - Computer Organization - Pipeline CPU design
9	8	1	26 days ago	NandFlashController/914	AXI Interface Nand Flash Controller (Sync mode)
9	2	0	20 days ago	OpenPhySyn/915	EDA physical synthesis optimization kit
9	5	0	5 years ago	Simple-32bit-ALU-Design/916	A simple, working, 32-bit ALU design.
9	1	2	1 year, 7 months ago	Nirah/917	Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
9	1	0	8 months ago	icestick-glitcher/918	Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit
9	2	0	1 year, 11 months ago	mips-pipeline/919	Mips Pipeline Processor
9	0	1	5 years ago	novena-spi-romulator/920	SPI romulator
9	1	1	7 years ago	uart_dpi/921	DPI module for UART-based console interaction with Verilator simulations
8	1	0	2 years ago	computer_architecture_class/922	Resources from my class on computer architecture design
8	1	0	7 years ago	rc4-prbs/923	A Verilog open-source implementation of a RC4 encryption algorigthm using a pseudorandom binary sequence (PRBS) for FPGA synthesis.
8	5	0	3 years ago	axi-ddr3/924	学习AXI接口，以及xilinx DDR3 IP使用
8	0	0	Unknown	flapga-mario/925	FlaPGA Mario - A flappy-bird like video game implemented in Verilog for Basys3
8	2	0	2 years ago	HUST-Verilog-Labs/926	HUST Verilog Labs 2018 and Digital logic labs 2018
8	6	0	3 years ago	alu-8bit/927	Verilog Code for an 8-bit ALU
8	5	0	Unknown	nexys2-verilog-samples/928	Some verilog examples to run on a Digilent Nexys2
8	5	0	2 years ago	ps2/929	PS2 interface
8	3	0	Unknown	vlsi681spring09/930	Class Project for 681 VLSI System Design Course at The University of Cincinnati, Spring 2009
8	7	0	Unknown	Amber-Marsohod2/931	Port of Amber ARM Core project to Marsohod2 platform
8	8	0	Unknown	SoC-Design-DDR3-Controller/932	DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
8	1	0	10 years ago	adat-verilog/933	Altera Cyclone FPGA cores for dealing with ADAT I/O, written in Verilog.
8	1	0	Unknown	cpld-6502/934	6502 CPU in 4 small CPLDs
8	1	1	Unknown	Chip-Design/935	Design and Verification of a Complete Application Specific Integrated Circuit
8	6	0	Unknown	CyNAPSEv11/936	The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
8	1	0	Unknown	i2cmon/937	FPGA-based I2C to RS-232 serial converter / bus monitor
8	4	0	Unknown	CPUonFPGA/938	It's a basic computer designed using VERILOG on XILINX FPGA architecture.
9	6	0	6 years ago	Ethernet-communication-VHDL/939	FPGA implementation of Real-time Ethernet communication using RMII Interface
8	3	0	3 years ago	Rocket-Chip/940	None
8	2	0	1 year, 10 months ago	mini16_cpu/941	Very small and high performance CPU
8	0	0	9 months ago	MiSTerTutorial/942	MiSTer Tutorial
8	1	0	9 months ago	qemu-hdl-cosim/943	VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
8	8	0	5 years ago	Multiported-RAM/944	Modular Multi-ported SRAM-based Memory
8	2	0	2 years ago	SpartanMini/945	A flexible, simple, yet powerful FPGA development board.
8	4	1	a month ago	KWS-SoC/946	This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
8	2	0	2 years ago	v8cpu/947	v8cpu is a simple multi-cycle von Neumann architecture 8-bit CPU in under 500 lines of Verilog.
8	2	1	2 years ago	sigma/948	None
8	2	0	6 years ago	cpu/949	fpga based cpu hackery
8	3	0	8 years ago	GestureRecognition_Verilog/950	Identifies ASL Hand Gesture for numbers using image processing in verilog
8	1	1	1 year, 5 days ago	plus4/951	FPGATED based plus4 implementation using Papilio Pro platform
8	1	0	10 months ago	MiSTer-Lightweight-Framework/952	Lightweight framework using MiSTer IO board for core developers
8	0	0	5 days ago	ctf-writeups/953	My CTF writeups
8	1	0	5 years ago	Pulse-Width-Modulation-IP/954	A PWM Module IP core written in Verilog, along with a firmware driver (developed for the Zynq-7000 Programmable SoC)
8	8	0	5 years ago	unambiguous-encapsulation/955	experiments relating to the encapsulation of data within other data
8	9	0	8 years ago	minimig_tc64/956	MiniMig for TurboChameleon64
8	2	0	3 years ago	GlitchHammer/957	A custom coprocessor and SoC for hardware security experiments in electronics.
8	3	0	1 year, 1 month ago	CortexM3_SoC/958	None
8	5	0	5 years ago	utrasound_mobile_fpga/959	fpga for utrasound mobile device
8	6	0	6 months ago	fpga-workshop/960	Workshop that is going to be given together with the UPduino dev board
8	2	0	8 years ago	Verilog-Spectrum-Analyzer/961	FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.
8	1	0	2 months ago	32BIT-MIPS-CPU/962	Use Verilog
8	1	0	4 years ago	Bresenham-Line-Drawing-Algorithm/963	Verilog implementation of Bresenham's line drawing algorithm.
8	0	1	3 years ago	mawg/964	Modulation and Arbitrary Waveform Generator
8	7	0	2 years ago	Viterbi-Decoder-in-Verilog/965	An efficient implementation of the Viterbi decoding algorithm in Verilog
8	2	0	10 months ago	Verilog-for-Dummies/966	Workshop
8	1	0	11 days ago	ice40_power/967	Power analysis of the ICE40UP5K-SG48 devices
8	3	0	3 years ago	ml-ahb-gen/968	A Verilog AMBA AHB Multilayer interconnect generator
8	3	0	1 year, 7 months ago	Atari7800_MiSTer/969	Atari 7800 for MiSTer
8	3	0	18 years ago	wb_dma/970	WISHBONE DMA/Bridge IP Core
8	3	0	2 years ago	sdio-device/971	None
8	1	0	4 years ago	i2c-eeprom/972	Controller for i2c EEPROM chip in Verilog for Mojo FPGA board
8	0	3	4 months ago	jtcontra/973	FPGA conversion of KONAMI's Contra PCB hardware
8	0	1	1 year, 5 months ago	SoC_CNN/974	Convolutional Neural Network Implemented in Verilog for System on Chip
8	5	0	1 year, 2 months ago	verilog-divider/975	a super-simple pipelined verilog divider. flexible to define stages
8	2	0	5 months ago	CNNAF-CNN-Accelerator/976	CNN-Accelerator based on FPGA developed by verilog HDL.
8	0	0	2 years ago	tiny_soc/977	Picorv32 SoC on the TinyFPGA BX, for games etc.
8	5	0	2 years ago	FIFO_-asynchronous/978	异步FIFO的内部实现
8	2	0	3 years ago	sp-i586/979	soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk contained in the SPI flash.
8	4	0	4 years ago	mmuart/980	Simple RS232 UART
8	5	1	2 years ago	M2GL025-Creative-Board/981	Igloo2 M2GL025 Creative Development Board
8	1	0	3 months ago	core_usb_uart/982	USB serial device (CDC-ACM)
8	2	0	6 months ago	wbpwmaudio/983	A wishbone controlled PWM (audio) controller
8	1	0	11 years ago	nova/984	H.264/AVC Baseline Decoder
8	1	0	3 years ago	netv2-fpga-hdcp-engine/985	HDCP cipher engine for the NeTV2 FPGA
8	3	0	4 years ago	riffa2/986	Full duplex version of https://github.com/KastnerRG/riffa/issues/30
8	8	3	2 years ago	Chips-Demo/987	Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.
8	3	7	5 months ago	scarv-cpu/988	SCARV: a side-channel hardened RISC-V platform
8	1	0	2 years ago	SystemVerilog-Implementation-of-DDR3-Controller/989	The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.
8	2	0	5 years ago	ECG-feature-extraction-using-DWT/990	Haar wavelet based Discrete wavelet transform for ECG feature extraction in Verilog
8	2	0	3 years ago	SimMIPS/991	a MIPS-based embedded system on FPGA
8	4	0	4 years ago	Verilog-Single-Cycle-Processor/992	Verilog
8	2	1	6 months ago	tv80/993	TV80 Z80-compatible microprocessor
8	2	0	2 years ago	Ice40JupiterAce/994	Simple Jupiter Ace implementation for the Ice40 (myStorm BlackIce)
8	2	0	9 years ago	virtexsquared/995	18-545 project: ARM-like SoC
8	4	0	5 years ago	adsb_cape/996	None
8	2	1	1 year, 13 days ago	sd_device/997	SD device emulator from ProjectVault
7	5	1	5 years ago	8PointDCT_Verilog/998	Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algorithms have been proposed over the last couple of decades to reduce the number of computations and memory requirements involved in the DCT computation algorithm. One of the algorithms is implemented here using Verilog HDL.
8	2	0	4 years ago	GuitarHeroFFE/999	Guitar Hero: Fast Fourier Edition. An MIT 6.111 final project that uses the power of the FPGA to play guitar hero with real guitars.
8	3	0	9 months ago	cpu_gs132/1000	Verilog code of Loongson's GS132 core

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