//--------------------Module_LED-----------------------------//
module LED(
    input CLK_12M,
    output FPGA_LEDR,
    output FPGA_LEDG,
    output FPGA_LEDB
);
//----------------------rst_n---------------------------------//
    reg rst_n;
    reg [6:0]cnt_rst;
    
    always@(posedge CLK_12M)
        if(cnt_rst==100)
            begin 
                rst_n <= 1'd1;
            end
        else cnt_rst <= cnt_rst + 1'd1;
        
//--------------------led_cnt-------------------------------//
    reg [27:0]cnt;
    
    always @ (posedge CLK_12M or negedge rst_n)
        if(!rst_n)
            begin
                cnt <= 28'd0;
            end
        else
            begin
                if(cnt == 28'd60000000)
                    cnt <= 28'd0;
                else 
                    cnt <= cnt + 1'd1;
            end
        
//--------------------led----------------------------------//
    reg ledr,ledg,ledb;
    
    always @ (posedge CLK_12M or negedge rst_n)
        begin
            if(!rst_n)
                begin
                    ledr <= 1'd1;
                    ledg <= 1'd1;
                    ledb <= 1'd1;
                end
            else if(((cnt > 0) || (cnt == 0)) &&  ((cnt < 28'd20000000) || (cnt == 28'd20000000)))
                begin
                    ledr <= 1'd0;
                    ledg <= 1'd1;
                    ledb <= 1'd1;
                end
            else if((cnt > 28'd20000000) &&  ((cnt < 28'd40000000) || (cnt == 28'd40000000)))
                begin
                    ledr <= 1'd1;
                    ledg <= 1'd0;
                    ledb <= 1'd1;                
                end
            else 
                begin
                    ledr <= 1'd1;
                    ledg <= 1'd1;
                    ledb <= 1'd0;
                end
        end
        
    assign FPGA_LEDR = ledr;
    assign FPGA_LEDG = ledg;
    assign FPGA_LEDB = ledb;
        
//--------------------endmodule-----------------------------//
endmodule